Integrated circuits are operated in environments where radiation-induced logic errors may occur, such as in outer space. In outer space, for example, high-energy protons or heavy ions (cosmic rays) are a type of radiation that can cause logic errors when impacting integrated circuits. In such environments, the integrated circuit is required to maintain data integrity during a single event upset (“SEU”). A single event upset is a radiation-induced error in the logic state of a signal within the integrated circuit. Such an error can result from the collision between a high-energy proton or a heavy ion and the semiconductor material that forms the integrated circuit. This type of collision produces a quantity of electron-hole pairs in circuitry within the integrated circuit that is generating the signal, with the quantity of electron-hole pairs being capable of altering the logic state of the signal.
Current mode logic (“CML”) is a differential logic family intended to be utilized for the transmission of high-speed data. FIG. 1 is a simplified schematic illustrating a conventional current mode logic buffer 100 that includes two NMOS transistors 102, 104, each transistor receiving a respective one of a pair of complementary input signals A, Ab, where Ab is a signal having a voltage level corresponding to the complementary logic state of the signal A. Each of the transistors 102, 104 is connected in series with a corresponding pull-up resistor 106, 108 between a supply voltage Vdd and a current source 110. In operation, in response to the input signals A, Ab the buffer 100 generates a pair of complementary output signals Y, Yb on drain nodes of the transistors 102, 104 that are coupled to the pull-up resistors 106, 108.
A single event upset 112 is functionally illustrated in FIG. 1 and corresponds to radiation impacting the buffer 100 at the drain node of the transistor 102. The radiation corresponds to the collision of a high-energy proton, heavy ion, or other atomic particle at this node. A collision has the effect of removing charge from the drain node of the transistor 102, as is functionally represented by a current source 112 in the figure. Note that for current mode logic circuitry, which utilizes only NMOS transistors, single event upsets 112 cause only the invalid logic condition (0,0) since such an event will only have the affect of removing charge from one of the nodes in the buffer, as will be appreciated by those skilled in the art.
The effect of the single event upset event 112 on the operation of the buffer 100 of FIG. 1 is illustrated in the signal diagram of FIG. 2 showing the complementary output signals Y, Yb as a function of time during the occurrence of the event 112. As shown in FIG. 2, initially the complementary output signals Y and Yb have complementary logic levels 1 and 0, respectively, at just before a time T1. Upon occurrence of the single event upset 112 at the drain node of transistor 102, however, which occurs at the time T1 in FIG. 2, both the complementary output signals Y, Yb go low (i.e., to a logic level 0) as illustrated in the signal diagram. As a result, the single event upset 112 causes both complementary output signals Y, Yb to have the same logic state 0, which is an invalid logic condition. The output signals Y, Yb are complementary signals so the logic states (1,0) or (0,1) are valid while the logic states (0,0) and (1,1) are invalid logic conditions. Note that the buffer 100 is an inverting buffer if output signals Y, Yb are taken from the opposite drain nodes and in the description below if output signals Y, Yb are the complement of the input signals A, Ab during normal operation then the buffer 100 is assumed to be an inverting buffer, as will be appreciated by those skilled in the art.
Such invalid logic conditions may, of course, result in improper operation of electronic circuitry (not shown) of which the buffer 100 is a part. Moreover, such an invalid logic condition will be propagated by subsequent conventional current mode logic buffers 100 that receive invalid complementary output signals Y, Yb having invalid logic levels. This is seen with reference to the schematic of the buffer 100 in FIG. 1 since the buffer will generate invalid complementary output signals Y, Yb if invalid states (1,1) or (0,0) for the input signals A, Ab are received by the buffer.
FIGS. 3A-3C depict the effects of the single event upset 112 on the buffer 100 and the propagation of invalid logic conditions by such conventional buffers. FIG. 3A shows the example discussed with reference to FIGS. 1 and 2. The buffer 100 receives valid complementary input signals A, Ab of (1,0) and outputs invalid output signals Y, Yb of (0,0) due to the single event upset 112. Due to the single event upset 112, however, the output signal Y changes from 1 to a 0 such that the buffer 100 outputs the invalid logic condition (0,0). Now, assume a second buffer designated 300 in FIG. 3B downstream of the buffer 100 receives the erroneous output signals (0,0) from the buffer 100. The buffer 300 is identical to buffer 100, and so from the schematic of the buffer 100 in FIG. 1 it is seen the buffer 300 will propagate the invalid logic condition (0,0) by outputting the invalid logic condition (1,1) in response thereto. This is shown in FIG. 3B, with the buffer 300 receiving output signals (0,0) from buffer 100 and in response to these output signals the buffer 300 generates output signals (1,1). A third buffer 302 downstream from buffer 300 is shown in FIG. 3C and receives the invalid logic condition (1,1) from buffer 300 and outputs the invalid logic condition (0,0) responsive to these inputs. This example shows how conventional CML buffers propagate invalid logic conditions.
Current mode logic circuits are extremely susceptible to single event upsets, as will be appreciated by those skilled in the art. FIG. 4 illustrates a conventional triple module redundancy (TMR) approach for “hardening” current mode logic circuitry. With the TMR approach, a hardened CML voter circuit 400 is utilized in combination with triple redundancy of the actual electronic circuitry contained in the system to be protected. The actual electronic circuitry corresponds to each of the modules 402a-c in FIG. 4.
The hardened CML voter circuit 400 implements the illustrated Boolean logic function, namely Z=AB+AC+BC where Z is the output of the voter and A, B, and C are the outputs from the modules 402 a-c, respectively. Each of the outputs A, B, and C corresponds to a differential pair of outputs as discussed with reference to the buffer 100 of FIG. 1. In operation, the voter circuit 400 outputs a logic 1 for the output Z when any two outputs A, B, and C from the modules 402 a-c are equal to a logic 1. Thus, if two or more of the modules 402a-c output a logic 1 for the outputs A, B, and C then the logic 1 provided by these two modules is assumed to be correct. The rationale for this is that while a single event upset may impact one of the modules 402 a-c the probability that such a single event upset will impact more than one of the modules is extremely low.
FIGS. 5A-B illustrate conventional logic circuitry for the voter circuit 400 of FIG. 4. FIG. 5A illustrates a conventional NOR-NOR voter circuit 500 formed by three two-input NOR gates 502a-c that receive the outputs A-C from the modules 402a-c, with outputs from these three NOR gates being applied to a single three-input NOR gate 504 that generates the output Z in response thereto. FIG. 5B illustrates a conventional NAND-NAND voter circuit 506 formed by three two-input NAND gates 508a-c and a single three-input NAND gate 510 interconnected in the same way as the corresponding NOR gates in the circuit 500 of FIG. 5A. In operation, the circuits 500 and 506 operate as just described for the voter circuit 400 of FIG. 4, namely to provide a logic 1 for the output Z whenever two of the inputs A-C are a logic 1.
There is a need for improved circuits and methods of preventing single event upsets in current mode logic systems.